For high performance semiconductors, there is a migration towards the use of metal gates in order to overcome problems with polysilicon depletion. The semiconducting nature of the polysilicon gate electrode causes band-bending or a potential well in the gate. Carriers are confined over the dimensions comparable to their wave lengths. Corresponding charge distributions in the polysilicon layer result in a finite bias-dependent nature of the gate electrode capacitance (C.sub.P), arising from the polysilicon depletion effect. As gate oxides get thinner, in conjunction with scaling in Complementary Metal Oxide Semiconductor (CMOS) technologies, the increase in gate oxide capacitance (C.sub.OX) makes C.sub.OX comparable to the capacitance of the polysilicon gate electrode over a range of gate bias near the threshold voltage of the device. This results in an undesirable overall reduction in total gate capacitance (C.sub.G).
This effect is even more critical when a semiconductor device is operating in an inversion mode of operation, and can cause a decrease in overall capacitance by approximately 30% if the carrier concentration in the polysilicon gate electrode is below 10.sup.20 /cm.sup.3. Too much doping, such as doping for P+ gates which can increase C.sub.P, causes threshold voltage (V.sub.t) instability.
It is known that use of a metal gate can eliminate the polysilicon depletion effect. It is also well known that polysilicon gates have a high resistivity resulting in the need for siliciding the gates to reduce the overall resistivity. In some design environments, where it is not possible or desirable to silicide all the gates, such as SRAMs where not all portions are silicided due to a need for metal interconnect layers, the high resistivity of polysilicon gates is a disadvantage. In addition, when fully depleted silicon on insulator (FDSOI) technology is used, it is not possible achieve optimum V.sub.t 's through the use of polysilicon gates at practical SOI thicknesses. In addition, the use of polysilicon gates is inconsistent with the use of high permittivity (high-k) metal oxide gate dielectrics, where a high-k value is generally greater than 3.9, in that the possibility exists for silicon from the polysilicon to react with the metal-oxide causing a contamination of the metal oxide gate dielectric affecting its high-k characteristics.
In CMOS technology, N+ poly and P+ poly are used as gates in NMOS and PMOS devices respectively. N+ poly and P+ poly correspond to work functions of 4.1 eV for N+ poly and 5.2 eV for P+ poly gates. Current device dimensions require a silicon channel doping of greater than 1E17/cm.sup.3 to avoid short channel effects. When replacing dual-doped silicon gates, a work function of the metal needs to be chosen. One known method has been to choose the metal such that it has a mid-gap work function which would allow for symmetric V.sub.t s for both NMOS and PMOS devices. However, due to the doping requirements needed to avoid short channel effects, a mid gap metal results in V.sub.t s which are large for low voltage, low power, high performance devices. Therefore, it is desirable to have a method for providing low V.sub.t s for both NMOS and PMOS devices.